The invention relates generally to computer system memory access operations and, more particularly, to the allocation of memory access bandwidth based on an access count priority scheme. Each device requesting access to system memory may be assigned an access count--the value of which determines the number of consecutive memory access cycles the device may use before a different device is allowed an opportunity to access memory.
Many current computer systems employ memory sharing architectures in which a plurality of devices share access to, and use of, a common system memory resource. For example, the system memory of a personal computer (PC) is typically shared by one or more central processing units (CPUs), one or more Accelerated Graphics Port (AGP) devices, one or more Peripheral Component Interconnect (PCI) devices, one or more Universal Serial Bus (USB) devices, and one or more embedded devices such as bus-to-bus bridge circuits and digital signal processors.
In some prior art computer systems, memory access is controlled by a memory control device which arbitrates between various requestors (i.e., devices seeking access to system memory) in a round-robin fashion. In these systems, a first requester is granted a single access followed by a second requester and so on. When all requesters have been granted access once, the process repeats. A drawback to conventional round-robin based arbitration schemes is that it may take a unacceptably long time to completely service/satisfy a requester having a multiple memory access transaction. In some other prior art computer systems, memory access is controlled by a memory control device which arbitrates between various requestors based on a requestor's assigned priority. In these systems, higher priority requesters are favored over lower priority requestors. A drawback to conventional priority based arbitration schemes is that high priority requesters may block lower priority requesters from gaining access to system memory for an unacceptably long time.
As the number of devices issuing memory access requests increases, it becomes ever more important to allocate memory bus bandwidth (i.e., share system memory) in an efficient manner. Thus, there is a need for a memory access control technique that efficiently services requestors issuing multiple access transactions without denying access to those requestors issuing single access transactions and/or low priority requesters for an unacceptably long time.